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CMOS ST-BUSTM FAMILY MT90820 Large Digital Switch (LDX) Advance Information
Features
* * * * * * * * * * * * 2,048 channel non-blocking switch Maintains frame integrity on concatenated channels. Per-channel selection of minimum or constant throughput delay Serial streams at 2.048, 4.096 or 8.192Mb/s Frame offset delay measurement Programmable frame delay offset Per-channel three-state control Per-channel message mode Control interface compatible to Intel/Motorola CPUs Block programming feature for connection memory ST-BUS/MVIP and GCI interfaces Test Port compatible to IEEE-1149.1 standard
ISSUE 1
May 1995
Ordering Information MT90820AP MT90820AL 84 Pin PLCC 100 Pin QFP
-40 to +85C
Description
The Large Digital Switch (LDX) is an advanced digital switch allowing the users to build up to 2048 channel non-blocking switch. The serial interface can be at 2, 4 or 8 Mb/s compatible to ST-BUS/MVIP/ HMVIP or GCI standards. The LDX can be programmed to provide either minimum or constant throughput delay on all its channels. The device also features three-state control and message mode on per-channel basis. To manage the problem of line delays, each input stream can have an individually programmed input frame offset delay. The offset delay can be calibrated with a dedicated frame measurement facility inside the device.
Applications
* * * * * * Medium and large switching platforms C.O. switches CTI application Voice/data multiplexer Digital cross connects ST-BUS/HMVIP interface functions
VDD VSS TMS TDI TDO
TCK TRSTB TEST RESETB
ODE
Test Port STi0 STi1 STi2 STi3 STi4 STi5 STi6 STi7 STi8 STi9 STi10 STi11 STi12 STi13 STi14 STi15 Output MUX STo0 STo1 STo2 STo3 STo4 STo5 STo6 STo7 STo8 STo9 STo10 STo11 STo12 STo13 STo14 STo15
Serial to Parallel Converter
Multiple Buffer Data Memory
Parallel to Serial Converter
Internal Registers
Connection Memory
Timing Unit
Microprocessor Interface
CLK FRM FE/ HMVIP HCLK
AS/ IM DS CS R/W ALE RD WR
A7-A0 DTA D15-D8/ CSTo AD7-AD0
Figure 1 - Functional Block Diagram
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Advance Information
10
8
6
4
2
84
82
80
78
STi0 STi1 STi2 STi3 STi4 STi5 STi6 STi7 STi8 STi9 STi10 STi11 STi12 STi13 STi14 STi15 FRM FE/HCLK VSS CLK VDD
76
VSS ST015 STo14 STo13 ST012 STo11 STo10 STo9 STo8 VDD VSS STo7 STo6 STo5 STo4 STo3 STo2 STo1 STo0 ODE VSS
12 14 16 18 20 22 24 26 28 30 46 48 34 36 38 40 42 44 50 32 52 74 72 70 68 66
84 PIN PLCC
64 62 60 58 56 54
CSTo DTA D15 D14 D13 D12 D11 D10 D9 D8 VSS VDD AD7 AD6 AD5 AD4 AD3 AD2 AD1 AD0 VSS
STi0 STi1 STi2 STi3 STi4 STi5 STi6 STi7 STi8 STi9 STi10 STi11 STi12 STi13 STi14 STi15 FRM FE/HCLK VSS CLK
80 82
NC NC NC NC VSS ST015 STo14 STo13 ST012 STo11 STo10 STo9 STo8 VDD VSS STo7 STo6 STo5 STo4 STo3 STo2 STo1 STo0 ODE VSS CSTo NC NC NC NC
78 76 74 72 70 68 66 64 62 60 58 56 54 52 50 48 84 46 86 44 88 42 90 92 94 36 96 34 98 32 100 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 40 38
TMS TDI TDO TCK TRSTB TEST RESETB HMVIP A0 A1 A2 A3 A4 A5 A6 A7 DS/RD R/W\RW CS AS/ALE IM
100 PIN PQFP
DTA D15 D14 D13 D12 D11 D10 D9 D8 VSS VDD AD7 AD6 AD5 AD4 AD3 AD2 AD1 AD0 VSS
2-180
NC NC NC NC VDD TMS TDI TDO TCK TRSTB TEST RESETB HMVIP A0 A1 A2 A3 A4 A5 A6 A7 DS/RD R/W\RW CS AS/ALE IM NC NC NC NC
Figure 2 - Pin Connections
Advance Information
Pin Description
Pin # 84 1, 11, 30, 54 64, 75 100 31, 41, 56, 66, 76, 99 5, 40, 67 68-75 81-96 97 Name VSS Ground. Description
CMOS
MT90820
2, 32, 63 3 - 10 12 27 28
VDD STo8 - 15 STi0 - 15 FRM
+5 Volt Power Supply. Data Stream Output 8 to 15: Serial data Output stream. These stream may have data rates of 2.048, 4.096 or 8.192 Mb/s. Data Stream Input 0 to 15: Serial data input stream. These stream may have data rates of 2.048, 4.096 or 8.192. Frame Pulse (input): This input accepts and automatically identifies frame synchronization signals formatted according to ST-BUS and GCI interface specifications, when HMVIP pin =0. When HMVIP pin =1, FRM input accepts a negative frame pulse which conforms to HMVIP formats. Frame Measurement input, when HMVIP pin = 0. 4.096MHz Clock input, when HMVIP pin = 1. Clock (input): Serial clock for shifting data in/out on the serial stream. When 1, enable test mode for production testing. Test Data Input. Test Data Output. Test Clock input. Test Reset Input: When 0, resets the test circuit. Internal Connection: keep at 0 for normal operation. Device Reset Input: When 0, resets the device. HMVIP mode input. When 1, enables HMVIP interface. When 0, the device operates in ST-BUS/GCI mode. Address 0 - 7(Input): When non-multiplexed CPU bus is selected, these lines provide the A0 - A7 address lines to internal memories. Data Strobe/Read (input): When non-multiplexed CPU bus or Motorola multiplexed bus are selected, this input is DS. This active high input works in conjunction with CSB to enable read and write operation. For Intel multiplexed bus, this input is RDB. This active low input sets the data bus lines (AD0-AD7, D8-D15) as outputs. Read/Write \ Write (Input): In case of non-multiplexed and Motorola multiplexed buses, this input is Read/Write. This input controls the direction of the data bus lines (AD0 - AD7, D8-D15) during a microprocessor access. Chip Select (Input): Active low input enabling a microprocessor access of the device.
29 31 33 34 35 36 37 38 39 40 41 48 49
98 100 6 7 8 9 10 11 12 13 14-21 22
FE/HCLK CLK TMS TDI TDO TCK TRSTB IC RESETB HMVIP A0 - A7 DS/RD
50
23
R/W\WR
51
24
CS
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Pin # 84 52 53 100 25 26
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Pin Description
Name AS/ALE IM Description Address Strobe or Latch Enable: This input is only used if multiplexed bus is selected. CPU Interface Mode (input): If High, this input selects the multiplexed microprocessor bus interface. If this input is not connected or grounded, the device resumes non-multiplexed bus interface. Address/Data Bus (Bidirectional): These are bi-directional data pins on the microprocessor interface. In the multiplexed bus mode, these pins also provide the input address to the internal registers and memories. Data Bus (Bidirectional): These are additional bi-directional data pins on the microprocessor interface. Data Acknowledgement (Open Drain Output): This active low output indicates that a data bus transfer is complete. A 10 kohm pull-up resistor is required at this output. Control Output (output). Output Device Enable (input): This is the output enable control for the STo0 to STo15 serial outputs. When this input is high, the STo0-15 output drivers function normally. If this input is low, Sto0-15 are in high impedance. Note: Even when ODE is high, each channel may still be put into high impedance state by using per channel control bit in the connection memory. Data Stream Output 0 to 7: Serial data Output stream. These streams may have data rates of 2.048, 4.096 or 8.192Mb/s. Unused pins.
55 62 65 72 73
32-39
AD0 - 7
42-49 50
D8 - 15 DTA
74 76
55 57
CSTo ODE
77 84 -
58-65 1 - 4, 27 30, 51 54 77 80
STo0 - 7 NC
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Device Overview
The LDX is capable of switching 2,048 x 2,048 channels. The device is designed to switch 64 or N x 64 kbit/s data. It can provide frame integrity for data applications and minimum throughput switching delay for voice application on a per channel basis. The serial input streams of LDX can operate at 2.048, 4.096 and 8.192 Mbit/s and are arranged in 125s wide frames which contains 32, 64 and 128 channels, respectively. The LDX automatically identifies the polarity of the input frame synchronization signal and configures the serial ports to be compatible to either ST-BUS and GCI formats. The input and output streams accept identical data rates only. By using Mitel message mode capability, the microprocessor can access input and output timeslots on a per channel basis to control external circuits or other ST-BUS devices. Two different microprocessor bus interface can be selected through an input mode pin (IM): Non-multiplexed or Multiplexed. These interfaces provide compatibility with Intel/National multiplexed and Motorola Multiplexed/Non-multiplexed buses. The frame offset calibration allows users to measure the frame offset delay using an frame evaluation pin (FE). The input stream offset delay can be individually programmed using internal registers.
CMOS
MT90820
Locations in the connect memory are associated with particular output streams. When a channel is due to be transmitted on an output, the data for the channel can either be switched from an input as in connection mode or it can be from the connect memory as in message mode. Data destined for a particular channel on the serial output stream is read from the data memory or connect memory during the previous channel time-slot. This allows enough time for memory access and parallel to serial conversion. Connection and Message Modes In Connection mode, the addresses of the inputs for all output channels are stored in the connect memory. Once the source addresses are programmed by the CPU, the contents of the data memory at the selected address are transferred to the parallel-to-serial inverters. By having the output channel specifying the source channel through the connect memory, the user can route the same input channel to serval output channels, allowing broadcast facility within the switch. In message mode, the CPU writes data to the connect memory locations corresponding to the output link and channel number. The lower half (8LSBs) of the connect memory content is transferred directly to the parallel-to-serial converter one channel before it is to be output. The data is transmitted on to the output every frame until it is changed by the CPU with a new data. The five most significant bits in the connect memory determine individual output channel to be in message or connection mode, select output throughput delay type, enable/disable output drivers and enable/disable the loopback mode. In addition, one of these bits allows the user to control the CSTo output. If an output channel is set to high-impedance, the TDM serial stream output will be in high impedance during that channel time. In addition to the perchannel control, all channels on the TDM outputs can be placed in high impedance by either pulling the ODE input pin low or programming a particular bit in the control register. The connect memory data is received via the microprocessor interface through the data I/O bus. The addressing of the LDX internal registers, data and connect memories is performed through address input pins and the Memory Select bit in the control register.
Functional Description
A functional Block Diagram of the LDX device is shown in Figure 1. Depending upon the application, the LDX device receives TDM serial data at different rates. Data and Connect Memory For all data rates, the received serial data is converted to parallel format by the serial to parallel converters and stored sequentially in a Data Memory. Depending upon the selected operation, the data memory may have up to 2,048 bytes in use. The sequential addressing of the data memory is performed by an internal counter which is reset by the input 8 kHz frame pulse (FRM) marking the frame boundaries of the incoming serial data streams. Data to be output on the serial streams may come from two sources: Data Memory or Connect Memory.
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input/16-output data streams with 64 64Kbit/s channels each. The modes allows 1,024 x 1,024 channel Switch Matrix configuration. The interface clock is 8.192MHz. Serial Links with Data Rates at 8.192 Mb/s When the 8.192Mb/s data rate is selected for input and output streams, the device is configured with 16input/16-output data streams with 128 64Kbit/s channels each. The modes allows 2,048 x 2,048 channel Switch Matrix configuration. The interface clock is at 16.384 MHz. Table 1 summarizes the switching configurations. Input Frame Offset Selection The LDX provides a feature called Input Frame Offset allowing users to compensate for the varying delays on the incoming serial inputs while building large switch matrices. Usually, different delays occur on the digital backplanes causing the data and frame pulse signal to be skewed at the input of the switch device. This may result in the system frame pulse to be active at the FRM input before the first bit of the frame is received at the serial input. The LDX allows users to compensate the input delay offset by programming the Frame Input Offset (FOS) registers. Each input stream can have its own delay offset value. Possible adjustment is up to 4 master clock periods forward with resolution of 1/2 clock period. Frame Alignment Evaluation To manage the problem of different data input delays (with respect to the frame pulse), the LDX provides the FE input for the frame alignment evaluation. The evaluation starts when the SFE bit in the IMS register is changed from low to high. Two frames later, the CFE bit of the frame alignment register (FAR) changes from low to high to signal the CPU
Serial Data Interface The master clock (CLK) can be either at 4.096, 8.192 or 16.384 MHz allowing serial data link operation at 2.048, 4.096 and 8.192 Mb/s respectively. The master clock frequency is always twice the data rate. The input and output streams accept identical data rate. The input 8 kHz frame pulse can be in either ST-BUS or GCI format. The LDX automatically detects the presence of an input frame pulse and identifies the type of serial interface. In ST-Bus format, every second falling edge of the master clock marks a bit boundary and the input data is clocked by the rising edge, three quarters of the way into the bit cell. In GCI format, every second rising edge of the master clock marks the bit boundary while data sampling is performed on the falling edge, at three quarters of the bit cell boundary.
Switching Configuration
Switching configurations are determined basically by the data rates selected at the serial inputs and outputs. To specify the switching configuration required, the Interface Mode Selection (IMS) register has to be initialized on system power-up. The switching configuration is selected by two DR bits in the IMS register. Serial Links with Data Rates at 2.048 Mb/s When the 2.048Mb/s data rate is selected for input and output streams, the device is configured with 16input/16-output data streams with 32 64Kbit/s channels each. The modes allows 512 x 512 channel Switch Matrix configuration. The interface clock is 4.096 MHz. Serial Links with Data Rates at 4.096 Mb/s When the 4.096 Mb/s data rate is selected for input and output streams, the device is configured with 16-
Serial Interface Data Rate 2 Mb/s 4 Mb/s 8 Mb/s
Master Clock Required (MHz) 4.096 8.192 16.384
Number of Input x Output Streams 16 x 16 16 x 16 16 x 16
Matrix Channel Capacity
Switch Matrix type
Input/Output Stream used
512 x 512 1,024 x 1,024 2,048 x 2,048
Non-Blocking Non-Blocking Non-Blocking
STi0-15/STo0-15 STi0-15/STo0-15 STi0-15/STo0-15
Table 1: Switching Configuration
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Advance Information
that a valid offset measurement is ready to be read from the FAR register. This feature is not available when the HMVIP interface is enabled, i.e. when HMVIP pin is tied to VDD.
CMOS
MT90820
connected HIGH, the internal parallel microport provides compatibility to MOTEL interface allowing direct connection to Intel, National and Motorola CPUs. The MOTEL circuit (MOtorola and inTEL compatible bus) automatically identifies the types of CPU Bus connected to the LDX. This circuit uses the level of the DS/RD input pin at the rising edge of the AS/ALE to identify the appropriate bus timing connected to the LDX. If DS/RD is low at the rising edge of AS/ ALE then Motorola bus timing is selected. If DS/RD is HIGH at the rising edge of AS/ALE, then the Intel bus timing is selected. The LDX microport provides the access to the internal registers, connect and data memories. All locations can be read or written except for the data memory which can be read only.
Memory Block Programming
The LDX device provides the capability of block programming the connect memory block. By using this feature, the five MSBs of the connect memory belonging to each output channel can be automatically programmed with a fixed pattern defined by the IMS register. This feature reduces the system initialization time. To enable the block programming mode, user have to set the Memory Block Program (MBP) bit of the control register to HIGH and program the IMS register with the Block Programming Enable (BPE) bit = 1, and the desired pattern. The block programming takes two frames to complete. Delay Through the LDX The switching of information from the input serial streams to the output serial streams results in a delay. Depending on the type of information to be switched, the LDX can be programmed to perform time-slot interchange functions with different throughput delay capabilities on the per-channel basis. For voice application, variable throughput delay can be selected ensuring minimum delay between input and output data. In wideband data applications, constant throughput delay can be selected maintaining the frame integrity of the information through the switch. The delay through the LDX varies according to the type of throughput delay selected in the connect memory.
Internal Register and Address Memory
To access internal registers, users have to connect the A7 pin to LOW. To access to data and connect memories positions, users have to connect the A7 pin HIGH. Table 2 summarizes the internal register and address memory mapping.
Initialization of the LDX
On initialization or power up, the contents of the connect memory can be in any states. This is a potentially hazardous condition when multiple LDXs outputs are tied together to form matrices, as these output may conflict each other. The ODE pin should be held low on power up to keep all outputs in the high impedance condition.
Microprocessor Port
The LDX provides an microprocessor interface with non-multiplexed and multiplexed bus structures. The LDX microport is compatible to Motorola multiplexed/ non-multiplexed and Intel multiplexed buses. The multiplexed bus structure is selected by the CPU interface Mode (IM) pin. When the IM pin is not connected (left open) or grounded, the LDX parallel port assumes the default Motorola non-multiplexed bus mode. If IM pin is
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A7
0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
CMOS
Advance Information
A6
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1
A5
0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 0 0 . 1 1
A4
0 0 0 0 0 0 0 0 0 . 1 1 0 0 . 1 1 0 0 . 1 1
A3
0 0 0 0 0 0 0 0 0 . 1 1 0 0 . 1 1 0 0 . 1 1
A2
0 0 0 0 1 1 1 0 0 . 1 1 0 0 . 1 1 0 0 . 1 1
A1
0 0 1 1 0 0 1 0 0 . 1 1 0 0 . 1 1 0 0 . 1 1
A0
0 1 0 1 0 1 0 0 1 . 0 1 0 1 . 0 1 0 1 . 0 1
Location
Control Register, CAR. Interface Mode Selection register, IMS Frame Alignment register, FAR Frame Input Offset register 0, FOS0 Frame Input Offset register 1, FOS1 Frame Input Offset register 2, FOS2 Frame Input Offset register 3, FOS3 Ch 0* Ch 1* . Ch 30* Ch 31* Ch 32** Ch 33** . Ch 62** Ch 63** Ch 64*** Ch 65*** . Ch 126*** Ch 127***
Note 1: The bit A7 must be retained HIGH for accesses to Data and Connection Memory positions. The bit A7 must be retained LOW for accesses to Registers. Note*: Channel 0 to 31 are used in 2Meg mode. Note**: Channel 0 to 63 are used in 4Meg mode. Note***: Channel 0 to 127 are used in 8Meg mode.
Table 2 - Internal Register and Address Memory Mapping
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Absolute Maximum Ratings*
Parameter 1 2 3 4 5
Supply Voltage Voltage on any pin I/O (other than supply pins) Current at digital outputs Package power dissipation Storage temperature
CMOS
MT90820
Max 6.0 Units V V mA W C
Symbol VDD V IO PD TST
Min
VSS - 0.3
VDD + 0.3
40 2
- 65
150
* Exceeding these figures may cause permanent damage. Functional operation under these conditions is not guaranteed.
Recommended Operating Conditions Characteristics 1 2 3 Operating Temperature Positive Supply Input Voltage
Voltages are with respect to ground (VSS) unless otherwise stated.
Sym TOP VDD VI
Min 4.75 4.75 0
Typ* 5.0 5.0
Max 5.25 5.25 VDD
Units C V V
Test Conditions
* Typical figures are at 25C and are for design aid only; not guaranteed and not subject to production testing.
DC Electrical Characteristics - Voltages are with respect to ground (VSS) unless otherwise stated.
Characteristics 1 2 3 4 5 6 7 8 9 10 11
O U T P U T S I N P U T S
Sym IDD VIH VIL IIL
Min
Typ 50
Max
Units mA V
Test Conditions Output unloaded
Supply Current Input Voltage High Input Voltage Low Input Leakage (input pins) Input Leakage (I/O pins) Input Pin Capacitance Output Voltage High Output Voltage Low Output High Current Output Low Current High Impedance Leakage Output Pin Capacitance
2.0 0.8 34 5 100
V A A pF V IOH = 10mA IOL = 5mA Sourcing. VOH=2.4V Sinking. VOL=0.4V VI between VSS and VDD
CI VOH VOL IOH IOL IOZ CO 10 5 2.4
8
0.4
V mA mA
5 8
A pF
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NOTES:
CMOS
Advance Information
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